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KM736FV4021 KM718FV4021
Document Title
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
128Kx36 & 256Kx18 SRAM
Revision History
Rev. No.
Rev. 0.0 Rev. 0.1
History
- Preliminary specification release - Change specification format. No change was made in parameters. - Updated IDD, ISB and Input High Level. Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions. For JTAG, updated Vendor Definition and added tSVCH/tCHSX. - Final specification release
Draft Date
Remark
Preliminary
April, 1997
Preliminary
Rev. 0.2
Jan. 1998
Preliminary
Rev. 1.0
Dec. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
128Kx36 & 256Kx18 SRAM
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
FEATURES
* * * * * * * * * * * * 128Kx36 or 256Kx18 Organizations. 3.3V Core Power Supply. LVTTL Input and Output Levels. Differential, PECL Clock Inputs K, K. Synchronous Read and Write Operation Registered Input and Registered Output Internal Pipeline Latches to Support Late Write. Byte Write Capability(four byte write selects, one for each 9bits) Synchronous or Asynchronous Output Enable. Power Down Mode via ZZ Signal. JTAG 1149.1 Compatible Test Access port. 119(7x17)Pin Ball Grid Array Package(14mmx22mm) Organization Part Number KM736FV4021H-5 128Kx36 KM736FV4021H-6 KM736FV4021H-7 KM718FV4021H-5 256Kx18 KM718FV4021H-6 KM718FV4021H-7 Cycle Time 5 6 7 5 6 7 Access Time 2.5 3.0 3.5 2.5 3.0 3.5
FUNCTIONAL BLOCK DIAGRAM
SA[0:16] or SA[0:17] CK SS SW Latch SWx Register SWx Register Latch SW Register SW Register Read Address Register 1 Write Address Register 0 Row Decoder 128Kx36 or 256Kx18 Array Column Decoder Write/Read Circuit
SWx (x=a, b, c, d) or (x=a, b)
0
1 Data In Register
SS Register
SS Register
Data Out Register
G ZZ K K CK DQx[1:9] (x=a, b, c, d) or (x=a, b)
PIN DESCRIPTION
Pin Name K, K SAn DQn SW SWa SWb SWc SWd ZZ VDD Pin Description Differential Clocks Synchronous Address Input Bi-directional Data Bus Synchronous Global Write Enable Synchronous Byte a Write Enable Synchronous Byte b Write Enable Synchronous Byte c Write Enable Synchronous Byte d Write Enable Asynchronous Power Down Core Power Supply Pin Name VDDQ M1, M2 G SS TCK TMS TDI TDO VSS NC Pin Description Output Power Supply Read Protocol Mode Pins ( M1=VSS, M2=VDD ) Asynchronous Output Enable Synchronous Select JTAG Test Clock JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Output GND No Connection
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
PACKAGE PIN CONFIGURATIONS(TOP VIEW)
KM736FV4021(128Kx36)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc8 DQc6 VDDQ DQc3 DQc1 VDDQ DQd1 DQd3 VDDQ DQd6 DQd8 NC NC VDDQ 2 SA13 NC SA12 DQc9 DQc7 DQc5 DQc4 DQc2 VDD DQd2 DQd4 DQd5 DQd7 DQd9 SA15 NC TMS 3 SA10 SA9 SA11 VSS VSS VSS SWc VSS NC VSS SWd VSS VSS VSS M1 SA14 TDI 4 NC NC VDD NC SS G NC NC VDD K K SW SA16 SA0 VDD SA1 TCK
128Kx36 & 256Kx18 SRAM
5 SA7 SA8 SA6 VSS VSS VSS SWb VSS NC VSS SWa VSS VSS VSS M2 SA3 TDO
6 SA4 NC SA5 DQb9 DQb7 DQb5 DQb4 DQb2 VDD DQa2 DQa4 DQa5 DQa7 DQa9 SA2 NC NC
7 VDDQ NC NC DQb8 DQb6 VDDQ DQb3 DQb1 VDDQ DQa1 DQa3 VDDQ DQa6 DQa8 NC ZZ VDDQ
KM718FV4021(256Kx18)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb1 NC VDDQ NC DQb4 VDDQ NC DQb6 VDDQ DQb8 NC NC NC VDDQ 2 SA13 NC SA12 NC DQb2 NC DQb3 NC VDD DQb5 NC DQb7 NC DQb9 SA15 SA17 TMS 3 SA10 SA9 SA11 VSS VSS VSS SWb VSS NC VSS NC VSS VSS VSS M1 SA14 TDI 4 NC NC VDD NC SS G NC NC VDD K K SW SA16 SA1 VDD NC TCK 5 SA7 SA8 SA6 VSS VSS VSS NC VSS NC VSS SWa VSS VSS VSS M2 SA3 TDO 6 SA4 NC SA5 DQa9 NC DQa7 NC DQa5 VDD NC DQa3 NC DQa2 NC SA2 SA0 NC 7 VDDQ NC NC NC DQa8 VDDQ DQa6 NC VDDQ DQa4 NC VDDQ NC DQa1 NC ZZ VDDQ
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 SRAM
The KM736FV4021 and KM718FV4021 are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072words of 36 bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology. Single differential PECL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the secondedge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this cycle, signaling that the SRAM should drive out the data. During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multiple SRAM cycles to perform a single read operation.
Write(Store) Operation
All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock, one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input. Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the SRAM array.
Low Power Dissipation Mode
During normal operation, asynchronous signal ZZ must be pulled low. Low Power Mode is enabled by switching ZZ high. When the SRAM is in Power Down Mode, the outputs will go to a Hi-Z state and the SRAM will draw standby current. SRAM data will be preserved and a recovery time(tZZR) is required before the SRAM resumes to normal operation.
TRUTH TABLE
K X X ZZ H L L L L L L L L L G X H L L X X X X X X SS X X H L L L L L L L SW X X X H L L L L L L SWa X X X X H L H H H L SWb X X X X H H L H H L SWc X X X X H H H L H L SWd X X X X H H H H L L DQa Hi-Z Hi-Z Hi-Z DOUT Hi-Z DIN Hi-Z Hi-Z Hi-Z DIN DQb Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z DIN Hi-Z Hi-Z DIN DQc Hi-Z Hi-Z Hi-Z DOUT Hi-Z Hi-Z Hi-Z DIN Hi-Z DIN DQd Hi-Z Hi-Z Hi-Z Operation Power Down Mode. No Operation Output Disabled. Output Disabled. No Operation
DOUT Read Cycle Hi-Z Hi-Z Hi-Z Hi-Z DIN DIN No Bytes Written Write first byte Write second byte Write third byte Write fourth byte Write all byte
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
ABSOLUTE MAXIMUM RATINGS
Parameter Core Supply Voltage Relative to VSS Output Supply Voltage Relative to VSS Voltage on any I/O pin Relative to VSS Maximum Power Dissipation Output Short-Circuit Current Operating Temperature Storage Temperature Symbol VDD VDDQ VTERM PD IOUT TOPR TSTG
128Kx36 & 256Kx18 SRAM
Value -0.5 to 3.9 VDD -0.5 to VDD+0.5 3 25 0 to 70 -55 to 125
Unit V V V W mA C C
Note
NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High Level Input Low Level PECL Clock Input High Level PECL Clock Input Low Level Operating Junction Temperature Symbol VDD VDDQ VIH VIL VIH-PECL VIL-PECL TJ Min 3.15 2.35 1.7 -0.3 2.135 1.490 10 Typ 3.3 2.5 Max 3.45 3.45 VDD+0.3 0.7 2.420 1.825 110 Unit V V V V V V C Note
DC CHARACTERISTICS
Parameter Average Power Supply Operating Current-x36 (VIN=VIH or VIL, ZZ & SS=VIL) Symbol IDD5 IDD6 IDD7 IDD5 IDD6 IDD7 Min Max 650 600 550 600 550 500 60 1 1 VDDQ 0.4 Unit mA Note 1, 2
Average Power Supply Operating Current-x18 (VIN=VIH or VIL, ZZ & SS=VIL) Power Supply Standby Current (VIN=VIH or VIL, ZZ=VIH) Input Leakage Current (VIN=VSS or VDD) Output Leakage Current (VOUT=VSS or VDDQ, ZZ=VIH, G=VIH) Output High Voltage(IOH=-4mA) for VDDQ=3.3V Output High Voltage(IOH=-4mA) for VDDQ=2.5V Output Low Voltage(IOL=4mA)
NOTE :1. Minimum cycle. IOUT=0mA. 2. 50% read cycles.
-
mA
1, 2
ISB ILI ILO VOH1 VOH2 VOL
-1 -1 2.4 2.0 VSS
mA A A V V
1
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance
NOTE : Periodically sampled and not 100% tested.(dV=0V, f=1MHz)
128Kx36 & 256Kx18 SRAM
Symbol CIN COUT
Typ 4 7
Max 5 8
Unit pF pF
AC TEST CONDITIONS
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Clock Input High/Low Level(PECL) Input Rise/Fall Time Clock Input Rise/Fall Time(PECL)
Input and Out Timing Reference Level Clock Input Timing Reference Level Symbol
AC TEST OUTPUT LOAD
Value 3.15~3.45 2.4~2.6 1.7/0.7 2.4/1.5 1.0/1.0 1.0/1.0 1.25
Cross Point Unit
VDD VDDQ VIH/VIL VIH/VIL TR/TF TR/TF
V V V V ns ns V V
Dout
Z0=50 20pF* 50
1.25V *Capacitive load consists of all components of the tester environment
AC CHARACTERISTICS
Parameter Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Output Valid Clock High to Output Hold Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time SW, SW[a:d] Setup Time SW, SW[a:d] Hold Time SS Setup Time SS Hold Time Clock High to Output Hi-Z Clock High to Output Low-Z G High to Output High-Z G Low to Output Low-Z G Low to Output Valid ZZ High to Power Down(Sleep Time) ZZ Low to Recovery(Wake-up Time) Symbol tKHKH tKHKL tKLKH tKHQV tKHQX tAVKH tKHAX tDVKH tKHDX tWVKH tKHWX tSVKH tKHSX tKHQZ tKHQX1 tGHQZ tGLQX tGLQV tZZE tZZR -5 Min 5.0 1.5 1.5 0.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.5 Max 2.5 2.5 2.5 2.5 5.0 5.0 Min 6.0 1.5 1.5 0.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.5 -6 Max 3.0 3.0 3.0 3.0 6.0 6.0 Min 7.0 1.5 1.5 0.5 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 0.5 0.5 -7 Max 3.5 3.5 3.5 3.5 7.0 7.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
128Kx36 & 256Kx18 SRAM
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)
1 2 3 4 5 6 7 8
K
tKHKH tAVKH tKHKL tKLKH tKHAX
SAn
A1
tSVKH
A2
tKHSX
A3
A4
A5
A4
A6
A7
SS
tWVKH tKHWX tWVKH tKHWX
SW
tWVKH tKHWX
SWx
tKHQV tKHQZ tDVKH tKHDX tKHDX tKHQX1 tKHQX
DQn
Q1
Q2
D3
D4
Q5
Q4
NOTE 1. D3 is the input data written in memory location A3. 2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)
1 2 3 4 5 6 7 8
K
tKHKH
SAn
A1
A2
A3
A4
A5
A4
A6
A7
G
SW
SWx
tGHQZ tGLQV tGLQX
DQn
Q1
Q2
D3
D4
Q5
Q4
NOTE 1. D3 is the input data written in memory location A3. 2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last
write cycle address.
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
128Kx36 & 256Kx18 SRAM
TIMING WAVEFORMS OF STANDBY CYCLES
1
2
3
4
5
6
7
8
K
tKHKH
SAn SS SW SWx
A1
A2
A1
A2
A3
tZZE
tZZR
ZZ
tKHQV tKHQV
DQn
Q1
Q2
Q1
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
128Kx36 & 256Kx18 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0 Instruction 0 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TDO Output
Notes
SAMPLE-Z Boundary Scan Register IDCODE Identification Register
1 2 1 3 4 3 3 3
SAMPLE-Z Boundary Scan Register BYPASS SAMPLE BYPASS BYPASS BYPASS Bypass Register Boundary Scan Register Bypass Register Bypass Register Bypass Register
SRAM CORE M1 M2
1 1 1
TDI
BYPASS Reg. Identification Reg. Instruction Reg. Control Signals
TDO
NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VSS when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states.
4. SAMPLE instruction dose not places DQs in Hi-Z.
TMS TCK
TAP Controller
TAP Controller State Diagram
1 0 Test Logic Reset 0 Run Test Idle
1 1
Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 Pause DR 1 Exit2 DR 1 Update DR 0
1 1 0 1
Select IR 0 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1
1
0
1
0 0
0 0 0
1
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
SCAN REGISTER DEFINITION
Part 128Kx36 256Kx18 Instruction Register 3 bits 3 bits Bypass Register 1 bits 1 bits
128Kx36 & 256Kx18 SRAM
ID Register 32 bits 32 bits
Boundary Scan 70 bits 51 bits
ID REGISTER DEFINITION
Part 128Kx36 256Kx18 Revision Number (31:28) 0000 0000 Part Configuration (27:18) 00101 00100 00110 00011 Vendor Definition (17:12) XXXXXX XXXXXX Samsung JEDEC Code (11: 1) 00001001110 00001001110 Start Bit(0) 1 1
BOUNDARY SCAN EXIT ORDER(x36)
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R SA9 NC SA10 SA11 SA12 SA13 DQc9 DQc8 DQc7 DQc6 DQc5 DQc4 DQc3 DQc2 DQc1 SWc NC SS NC NC SW SWd DQd1 DQd2 DQd3 DQd4 DQd5 DQd6 DQd7 DQd8 DQd9 SA14 SA15 SA16 M1 SA8 NC SA7 SA6 SA5 SA4 DQb9 DQb8 DQb7 DQb6 DQb5 DQb4 DQb3 DQb2 DQb1 SWb G K K SWa DQa1 DQa2 DQa3 DQa4 DQa5 DQa6 DQa7 DQa8 DQa9 ZZ SA3 SA2 SA1 SA0 M2 5B 6B 5A 5C 6C 6A 6D 7D 6E 7E 6F 6G 7G 6H 7H 5G 4F 4K 4L 5L 7K 6K 7L 6L 6M 7N 6N 7P 6P 7T 5T 6R 4T 4P 5R 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOUNDARY SCAN EXIT ORDER(x18)
26 27 28 29 30 31 32 33 3B 2B 3A 3C 2C 2A 1D 2E SA9 NC SA10 SA11 SA12 SA13 DQb1 DQb2 DQa8 DQa7 34 2G DQb3 DQa6 DQa5 35 36 37 38 39 40 41 1H 3G 4D 4E 4G 4H 4M DQb4 SWb NC SS NC NC SW G K K SWa DQa4 4F 4K 4L 5L 7K 14 13 12 11 10 7G 6H 16 15 7E 6F 18 17 SA8 NC SA7 SA6 SA5 SA4 DQa9 5B 6B 5A 5C 6C 6A 6D 25 24 23 22 21 20 19
42 43 44 45
2K 1L 2M 1N
DQb5 DQb6 DQb7 DQb8
DQa3
6L
9
DQa2 DQa1 ZZ
6N 7P 7T 5T 6R 4P 6T 5R
8 7 6 5 4 3 2 1
46 47 48 49 50 51
2P 3T 2R 4N 2T 3R
DQb9 SA14 SA15 SA16 SA17 M1
SA3 SA2 SA1 SA0 M2
NOTE : 1. Pins 6B and 2B are no connection pin to internal chip. These pins are place holders for 16M part and the scanned data are fixed to "0" for this 4M parts.
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
JTAG DC OPERATING CONDITIONS
Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(IOH=-2mA) Output Low Voltage(IOL=2mA) Symbol VDD VIH VIL VOH VOL Min 3.15 2.0 -0.3 2.4 VSS
128Kx36 & 256Kx18 SRAM
Typ 3.3 -
Max 3.45 VDD+0.3 0.8 VDD 0.4
Unit V V V V V
Note
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
Symbol VIH/VIL TR/TF
Min 3.0/0.0 2.0/2.0 1.5
Unit V ns V
Note
1
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min 50 20 20 5 5 5 5 5 5 0 Max 10 Unit ns ns ns ns ns ns ns ns ns ns Note
JTAG TIMING DIAGRAM
TCK
tCHCH tMVCH tCHMX tCHCL tCLCH
TMS
tDVCH tCHDX
TDI
tCLQV
TDO
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Rev 1.0 Dec. 1998
KM736FV4021 KM718FV4021
119 BGA PACKAGE DIMENSIONS
14.000.10
128Kx36 & 256Kx18 SRAM
1.27
1.27
22.000.10 Indicator of Ball(1A) Location
20.500.10
C1.00
C0.70 0.7500.15
0.600.10 12.500.10
1.50REF 0.600.10
NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX.
119 BGA PACKAGE THERMAL CHARACTERISTICS
Parameter Junction to Ambient(at air flow of 1m/sec) Junction to Case Junction to Solder Ball Symbol Theta_JA Theta_JC Theta_JB Min Typ Max 17 4 10 Unit C/W C/W C/W Note
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Rev 1.0 Dec. 1998

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